Generally, a circuit system has multiple integrated circuit packages placed on a printed circuit board (PCB). Each integrated circuit package is coupled to the printed circuit board using a particular type of interconnect structure. Commonly known interconnect structures at the package/PCB interface include ball grid arrays (BGAs), land grid arrays (LGAs), pin grid arrays (PGAs) and surface mounted technology (SMT) pins.
However, these interconnect structures may not be able to support a high-speed circuit system (e.g., a circuit system with a data transfer rate that is greater than 25 gigabits per second (Gbps)). Such a limitation may be due to: (i) dimension mismatches between structures utilized to transmit signals within a package substrate and at the package/PCB interface, and (ii) parasitic inductances of the interconnect structures.
In most interconnect structures, the largest dimension mismatch is observed between a micro-via, a plated through-hole (PTH) via, and a BGA ball. Parasitic inductance may be an intrinsic characteristic of a pin that forms part of the interconnect structure. The parasitic inductance causes an inductive impedance mismatch for a transmitted signal. Hence, the two limitations can reduce the bandwidth of the interconnect structures and can increase unwanted higher-order mode signal problems in a high-speed circuit system.
The above-mentioned problems are sometimes resolved using micro-wave interconnect technology. However, micro-wave interconnect technology generally involves a large diameter (i.e., 3 millimeter (mm)) as a result of similar designs to a coaxial pin structure. This significantly reduces channel density between an integrated circuit package and a printed circuit board.